1. Field of the Invention
This invention relates to the field of operational amplifier offset voltage (V.sub.os) trimming techniques, and particularly to V.sub.os trimming for op amps with rail-to-rail input stages.
2. Description of the Related Art
"Input offset voltage" (V.sub.os) is a parameter associated with operational amplifiers (op amps), defined as the output voltage produced by the op amp when its differential input voltage is zero. An untrimmed V.sub.os can be on the order of millivolts, which appears as an error in the amplifier's output. When a highly accurate op amp is needed, a trimming method is typically used to make V.sub.os as small as possible; such methods include laser trimming a resistor during assembly, and applying a fixed "trim current" to a particular circuit node.
Rail-to-rail op amps, i.e., op amps which function for input signals that vary up to the amplifier's positive and negative supply voltages, pose an especially troublesome trimming problem. This is because such op amps typically employ complementary differential pairs, instead of the single differential pair found in conventional amplifiers. Each of the two differential pairs has a respective offset voltage, with the degree to which the amplifier's output is affected by the offset voltages being dependent on which of the pairs is conducting at any given time.
A conventional rail-to-rail op amp is shown in FIG. 1. The gates of a first differential pair of transistors M1 and M2 are connected across the amplifier's differential input terminals V.sub.in+ and V.sub.in- ; M1 and M2 are biased with a current source I1 connected between their respective sources and a negative supply voltage V.sub.SS. A second pair of transistors M3 and M4 are also connected across V.sub.in+ and V.sub.in-, and are biased with a current source I2 connected between their respective sources and positive supply voltage V.sub.DD. Each pair produces a respective differential output current between its two drain terminals. All four drain terminals are connected to an output stage 10, which converts the differential output currents to a single ended output current I.sub.OUT.
In the circuit shown in FIG. 1, M1 and M2 are n-channel FETs having their sources referenced to V.sub.SS, and M3 and M4 are p-channel FETs having their sources referenced to V.sub.SS, enabling the amplifier to handle rail-to-rail input voltages. Both pairs of transistors are active at the same time, except when the input common-mode voltage (V.sub.cm) is close to either rail. One of the pairs turns off when this occurs, because its transistors' gate-to-source voltages (V.sub.gs) become less than their threshold voltages (V.sub.T). Thus, only M1 and M2 are active if V.sub.cm is above about V.sub.DD -1 volt, and only M3 and M4 are active if V.sub.cm is below about V.sub.SS +1 volt.
As noted above, both differential pairs contribute to the amplifier's offset voltage. V.sub.os is fairly constant over that portion of the common-mode input range for which both pairs are active, and this V.sub.os value can be reduced by trimming. Unfortunately, V.sub.os will change when one or the other of the pairs stop conducting near the supply rail. When this occurs, the trim adjustment made to correct V.sub.os when both pairs are active is now incorrect, and V.sub.os will increase.
Another known rail-to-rail op amp is disclosed in U.S. Pat. No. 5,610,557 to Jett, Jr., and is shown in FIG. 2. Two complementary differential pairs 20 and 22 are connected across the amplifier's differential input terminals V.sub.in+ and V.sub.in-. A constant current source I3 biases differential pair 22, and a constant current source 24 biases differential pair 20. A transistor Q.sub.steer is connected between I3 and current source 24, and receives a reference voltage V.sub.ref at its base. When Q.sub.steer is not conducting, pair 22 receives bias current I3 and is active. When Q.sub.steer begins to conduct, at a common-mode input voltage established by the value of V.sub.ref, I3 is diverted to current source 24, disabling pair 22 and activating pair 20. Thus, only one pair is active at a time over most of the amplifier's common-mode input range.
The collector currents of the two pairs are connected to an output stage 26, which converts the two differential currents to a single-ended output current I.sub.out. A V.sub.os trimming capability is provided by four variable resistors R1-R4 in output stage 26. R1 and R2 are adjusted to trim V.sub.os when pair 20 is active, and R3 and R4 trim V.sub.os when pair 22 is active. There are several drawbacks to this trimming approach, however. The trim currents provided by R1-R4 are always present regardless of which differential pair is active, and while a pair's respective trim currents may be appropriate when its pair is active, they are unlikely to be ideal when the other pair is active. Furthermore, R1/R2 and R3/R4 are adjusted when their respective pairs are fully conducting. However, there is a transition region over which one pair stops conducting while the other pair starts conducting. Because the fixed trim currents provided by R1-R4 are adjusted to correct V.sub.os for common-mode voltages on either side of the transition region, the amplifier's V.sub.os --and the inaccuracy of I.sub.out --increases for common-mode input voltages that fall within the transition region.